Binary BCH for NAND Flash
ECC Tek's current binary BCH encoder and decoder designs for NAND Flash correct up to t=72 bits in error in 512 or 1024-byte pages.
ECC Tek's binary BCH encoder and decoder designs for NAND Flash allow customers to create customized binary BCH decoder designs by selecting various different decoder components. Each combination results in a decoder with unique performance characteristics.
Customers can choose components so that the decoder has a minimum gate count or a minimum latency.
Customers can also choose to have a fixed decoder delay or a delay which varies with the number of bits in error. With a variable delay decoder, if no errors are detected in the received word, the decoder delay is only 6 clock cycles and will increase as the number of errors increases. With a fixed delay decoder, the decoder latency is constant and equal to the longest delay. The advantage of a fixed delay is that the output will always be available at the same time regardless of the number of errors that occur.
Customers who wish to temporarily pause the data output from the decoder can implement a pause FIFO at the output at the decoder or ECC Tek can implement the pause FIFO for them.
Customers can synthesize the binary BCH encoder and decoder synthesizable Verilog code into one programmable encoder and decoder circuit that can handle various t and K values or they can synthesize the Verilog code into separate encoder and decoder circuits for specific t and K values.
ECC Tek has set the standard in space with parallel Reed-Solomon (PRS) encoders and decoders and is now setting the standard for NAND Flash with configurable binary BCH encoder and decoder designs.
A binary BCH encoder block diagram is shown below. Inputs and out data streams are "bytes".
A binary BCH decoder block diagram is shown below. Input and output data streams are "bytes".