ECC Design Tools

Numerous ECC design tools written in C were developed to automatically generate synthesizable Verilog code.  They significally accelerate the design process because the Verilog code created by the tools is guaranteed to be correct.  Developing Verilog code manually is exceedingly time-consuming and when you are done, it normally contains many errors which can be extremely time-consuming to find and correct.  In addition, some of the designs require a very large amount of Verilog code which would be extremely difficult and time-consuming to create manually and would almost surely contain many errors.

For each function block, there is a program to generate synthesizable Verilog code with any level of parallelism and any number of bits per symbol.

They are called SYNgen, PPUgen, PPU_PIPEgen, EVALgen, XORgen, ENCODERgen, etc.

In addition, there are programs to build the generator polynomial and a program to test and validate the design.