bBCH for Flash3

This is an overview of digital logic designs for encoding and decoding six Binary BCH (bBCH) codes which can correct t = 16, 24, 30, 40, 48, or 60 bits in error for use with NAND Flash memory chips with data field sizes in two ranges.  The first data field range (range 0) allows data fields of lengths  K = 512 to 519 bytes, and the second range (range 1) allows data field lengths of K = 1024 to 1031 bytes.  The t, K and range values are selected by inputs to the decoder.

The decoder is designed with enough parallelism to correct all correctable error patterns “on-the-fly” with no slowdown or pausing of continuous input data.

The BCH code being used is binary and serial encoders for binary codes input and output one bit at a time and serial syndrome calculators input one bit at a time.  For this design the encoder and decoder input and output 8 bits at a time.

Capital letters in the following Tables are variables measured in bytes and lower case letters are variables measured in bits.

The following table shows selectable values for t and the number of redundant bits, r, needed before adjustment is made to make codewords an even number of bytes.  The number of bits of redundancy, r = 14t.

The following Table shows the number of "bytes" of redundancy.

The decoder has a variable latency/delay which varies with the number of errors being corrected.

The i_range input selects either range 0 or range 1.

The i_sel_t input selects t = 16, 24, 30, 40, 48 or 60.

The value selected for K depends upon the range and the i_k_delta inputs.

The value for K = K_base_value + i_k_delta.  K_base_value = 512 for range 0 and 1024 for range 1.  i_k_delta is a 3-bit value so K can range from 512 to 519 for range 0 and from 1024 to 1031 for range 1.