RS ECC for pHDDs

The following drawing is a block diagram of a parallelized and pipelined RS errror correction system used to create failure-tolerant pHDDs.  The encoder is very simple.  All of the synthesizable Verilog code can be easily and quickly created using the ECC tools I developed for any possible configuration.

SYN stands for Syndrome Generator, PPU stands for Polynomial Processing Unit, INIT stands for Initialization of the error locator and error evaluator polynomials, EVAL stands for Evaluation of the error locator and error evaluator polynomials and XOR stands for Exclusive Or.

For wide systems, the decoder Verilog code becomes very large, and it is essential to have it generated by software.

When HDAs are used as the memory components, FIFOs need to be added at the outputs of the HDAs to accomodate variations in synthronization.