bBCH for Flash1

This design is configurable where six values for t and three values for K can be selected as shown below.  R and N are determined by K and t.  The amount of redundancy is adjusted so that R is an even number of bytes.  This is one of three bBCH designs developed for NAND Flash.

Serial bBCH designs input one bit at a time.  This implementation is partially-parallelized to input and output 8-bits at a time.This document describes digital logic designs for encoding and decoding Binary BCH (BBCH) codes which can correct 7, 8, 14, 15, 17, or 18 bits in error for use with Flash memory chips with page sizes of 514, 515 or 516 bytes.  The encoder adds from 12 to 30 bytes of redundancy onto each message (or data field).

The BCH codes being used are binary and usually encoders for binary codes input and output 1 bit a time and syndrome calculators input 1 bit at a time.  For this design the encoder and decoder input and output 8 bits a time and appear, from the outside, to be a Reed-Solomon (RS) encoder and decoder operating on 8-bit symbols.

Because of the similarity to the RS designs, much of the Verilog code that was used for InCOMM’s RS encoder and decoder is also used for the BBCH encoder and decoder.  This is beneficial because if one understands one design, they are well on their way to understanding the other design.

The BBCH encoder and decoder have inputs which are used to select values for K, the data field size, of 514, 515 or 516 bytes and t, the number of bits to correct, of 7, 8, 14, 15, 17 or 18 bits.  Capital letters in the following Tables are variables measured in bytes and lower case letters are variables measured in bits.  Selectable values for k in bits are 4,112, 4,120 or 4,128 bits.

The folowing Table shows selectable values for t, r, n and k in bits before adjustment is made to make codewords an even number of bytes.

The number of bits of redundancy, r, added to a message for each value of t as shown in the above Table was adjusted by multiplying the binary BCH generator polynomials by factors of low degree so that the adjusted amount of redundancy is a multiple of 8 and therefore is an even number of bytes which greatly simplifies the design of the encoder and decoder.  Selectable values for r, k and n in bits after the adjustment are shown below.

Selectable values for R, K and N in bytes after adjustment are shown in the Table below.