bBCH for Flash2

Digital logic designs for encoding and decoding binary BCH (bBCH) codes which can correct t = 16, 24, 25, 28, 29, or 30 bits in error for use with NAND Flash memory chips with data field sizes of from K = 1024, 1025, …, 1053 bytes.  The encoder adds from 28 to 53 bytes of redundancy onto each data field.  The decoder handles 81 (t, K) options where the total number of bytes in a codeword, N, is limited to 1081 or less as shown in Table 3.  The limitation on N could easily be changed if needed.

The BCH codes being used are binary and usually encoders for binary codes input and output 1 bit at a time and syndrome calculators input 1 bit at a time.  For this design the encoder and decoder input and output 8 bits at a time and appear, from the outside, to be a Reed-Solomon (RS) encoder and decoder operating on 8-bit symbols.

Capital letters in the following Tables are variables measured in bytes and lower case letters are variables measured in bits.

The first Table shows selectable values for t and the number of redundant bits, r, needed before adjustment is made to make codewords an even number of bytes.

The number of bits of redundancy, r, added to a message for each value of t as shown above was adjusted by multiplying the binary BCH generator polynomials by irreducible binary polynomials of low degree so that the adjusted amount of redundancy is a multiple of 8 and therefore is an even number of bytes which simplifies the design of the encoder and decoder.  Selectable values t and R are shown in the Table below.

The Table below shows all the 81 legitimate t, R, K and N options.