Simulation and Testing Programs

I developed simulation and testing programs written in C that can be configured to simulate and test any RS or bBCH encoder and decoder.  The programs are important tools in developing new designs in Verilog because they can be used to verify the operation of the Verilog encoder and decoder and to provide expected results for Verilog testbenches.  When the encoder and decoder Verilog code is correct, the results of running Verilog simulations produce results that are bit-for-bit equivalent to the results produced by the C code.  That's how the Verilog code is debugged.

In additon, the testing functions allow billions of error patterns to be operated on by the decoder to validate the decoder operation.