RS for pSSD1

The following drawing is a top level drawing of the parallel RS system licensed to NASA for use in the James Webb Space Telescope and several other missions.  The decoder corrects two chip failures (NASA actually uses synchronous DRAM chips rather than Flash) and detects many combinations of 3 or more symbol errors or chip failures.  The same design was licensed to a number of other companies and, to the best of my knowledge, has become the de facto standard for space both in the United States and Europe.  The chips are x4 chips and the system can correct for two chip failures.  If erasure correction had been implemented, four chip failures could have been corrected.  Another similar design was also licensed.  Several other RS designs were developed for NASA.

The following drawings are from the final document for the original design which was developed around 20 years ago.  This design is being used in numerous spacecraft including the James Webb Space Telescope.  The drawing below is the original top level drawing.

The drawing below is the encoder.

The drawing below is the original drawing for the decoder.

The synthesizable Verilog code for the original design can be licensed or the ECC design tools can be licensed to recreate an equivalent design.

Here's the overall general idea for any spacecraft.